HAUKI OS: Broadcom Tigon3 (BCM57xx) Network Architecture

Target Hardware: Broadcom NetXtreme BCM5751 Gigabit Ethernet (PCI Vendor: 0x14E4)
Validation Node: 'elli' (HP Compaq dx6100 MT, Pentium 4)

1. Mailbox DMA Architecture

Unlike Intel E1000's tail-pointer rings, the Broadcom Tigon3 series utilizes a Mailbox synchronization mechanism.

TX Mailbox (Producer Index): MMIO Offset 0x0300

RX Mailbox (Return Index): MMIO Offset 0x0200

The driver updates a 16-byte Buffer Descriptor (BD) in RAM, then writes the new index to the respective mailbox to notify the ASIC's internal microcontroller to fetch the frame via DMA.

2. Initialization Sequence

PCI Bus Scan: Due to motherboard bridging (especially on early PCIe architecture like the HP dx6100), the Broadcom silicon may reside on higher buses (e.g., Bus 64 / 0x40). A deep PCI scan is required.

Bus Mastering: The driver must force-enable Bus Mastering by writing 0x06 to the PCI Command Register (Offset 0x04).

MMIO Lock: Base address extracted from BAR0 (Offset 0x10).

3. Buffer Descriptor (BD) Structure

The hardware requires strictly 16-byte aligned packed structures:

C
struct tg3_tx_desc {
    unsigned int addr_high;
    unsigned int addr_low;
    unsigned short len;
    unsigned short flags;
    unsigned int vlan_tag;
} __attribute__((packed));


Note: Packet End Flag (0x0004) must be asserted in the flags field to prevent the ASIC from waiting for fragmented descriptor chains.

4. Execution Vector (The DMA Resurrection)

Testing volatile MMIO writes natively risks hard kernel panics. Development was accelerated by using a stable RTL8139 driver to listen on UDP port 1337. The compiled Broadcom kernel was blasted into memory via DMA, followed by a kexec jump to 0x50000, achieving headless, live kernel hot-swapping without hardware reboots.